1. Technical Field
The present invention is related to a gate driving apparatus.
2. Description of Related Art
Referring to FIG. 1, FIG. 1 is a block diagram illustrating a conventional gate driving apparatus 100. The conventional gate driving apparatus 100 includes two gate driving chips 110 and 120 which are connected in series with each other. The gate driving chip 110 has an input pin INPAD1 and an output pin OUPAD1, the gate driving chip 120 has an input pin INPAD2 and an output pin OUPAD2. Wherein, the output pin OUPAD1 of the gate driving chip 110 is coupled to the input pin INPAD2 of the gate driving chip 120, and the input pin INPAD1 of the gate driving chip 110 receives a voltage VB. A bias voltage circuit 112 of the gate driving chip 110 receives the voltage VB through the input pin INPAD1, and a functional block circuit 111 of the gate driving chip 110 generates an output signal (a gate driving signal) GD1 according to the voltage VB. Furthermore, in the gate driving chip 110, the input pin INPAD1 and the output pin OUPAD1 interconnects, and the voltage VB is transmitted to the bias voltage circuit 122 of the gate driving chip 120 from the input pin INPAD1 through the output pin OUPAD1.
Two functional block circuits 111 and 121 respectively generate two output signals GD1 and GD2 according two currents I1 and I2, wherein the currents I1 and I2 are respectively generated by two bias voltage circuits 112 and 122 according to the voltage VB. However, due to the variation of the process parameters between the gate driving chips 110 and 120, the currents I1 and I2 generated by the bias voltage circuits 112 and 122 according to the voltage VB may not be uniform. Therefore, the output signals GD1 and GD2 generated respectively by the functional block circuits 111 and 121 are not uniform.